This invention relates to methods for evaluating electronic components. More particularly, the invention relates to methods for evaluating systems of electronic components such as circuit board assemblies, backplanes, etc., using an application specific integrated circuit (ASIC) evaluation tool.
Semi-custom integrated circuit devices known generally as ASICs have become popular with electronic system designers. These devices are highly complicated integrated circuits that allow some degree of customization of the circuitry contained therein. Using one or more ASICs specially designed for an application, a system designer can dramatically reduce the number of electronic components (i.e., integrated circuit devices and other electronic parts) required to build an electronic system.
ASICs are available in a number of different technologies and in a variety of forms. Two primary forms of ASIC are widely available: gate-arrays and standard cell ASICs. Gate-arrays are basically an array of pre-integrated transistors (xe2x80x9csea of gatesxe2x80x9d) and input/output pads (I/O pads) on an integrated circuit chip without interconnecting conductors. The ASIC manufacturer supplies the ASIC user with a set of standard circuits blocks (typically gates, flip-flops, multiplexers, decoders, counters, shift-registers, etc.) which may be constructed from these transistors and I/O pads and which the user employs to specify the circuitry to be contained on the ASIC in the form of a circuit diagram. Only those circuit blocks which may be readily built from xe2x80x9cstandardxe2x80x9d transistors in the array can be offered. These circuit blocks represent the interconnections required between a set of transistors and/or I/O pad required to construct the circuit which will perform their respective functions. The interconnection of these transistors and I/O pads is accomplished by the ASIC manufacturer according to the user""s circuit diagrams. After interconnecting conductors have been applied to the ASIC, the ASIC is packaged, tested, and shipped to the user.
Standard-cell ASICs are similar to gate-arrays, from the user""s point of view, except that a wider variety of circuit blocks is available. The user employs a set of standard pre-defined circuit blocks to specify the circuity to be incorporated into a standard-cell ASIC in the form of the circuit diagram. In the case of standard-cell ASICs, however, no pre-integrated structures typically exist. The pre-defined circuit blocks used by the user to at define his circuitry represent complete circuit modules to be integrated onto a integrated circuit chip. Since xe2x80x9cstandardxe2x80x9d transistors are not a limiting factor, as they are for gate-arrays, circuit geometries may be optimized for each circuit module represented by a circuit block, allowing a much wider variety of circuit blocks to be offered to the user. These circuit blocks are arranged onto a xe2x80x9cblankxe2x80x9d integrated circuit chip in xe2x80x9ccookie cutterxe2x80x9d fashion by the ASIC manufacturer according to the circuit diagram supplied by the ASIC user. As with gate-arrays, after the standard cell integration process is completed, the chips are packaged, tested and shipped to the user.
In a variation on the standard-cell theme, many ASIC manufacturers offer xe2x80x9ccore-cells,xe2x80x9d typically very large and complicated circuits (e.g., microprocessors, peripheral controllers, etc.) which may be incorporated into an ASIC design as yet another circuit block, albeit a very large one. These core-cells are typically used in conjunction with other xe2x80x9csurrounding logicxe2x80x9d on an ASIC to perform an application-specific function. ASICs incorporating a core-cell and surrounding logic are called xe2x80x9ccore-cell-based ASICs.xe2x80x9d
Some very large gate-based circuit blocks similar to core cells are offered for gate-arrays, as well. While core-cells for gate arrays do not generally offer the same range of function, they can be extremely complicated gate-based designs. Gate-arrays making use of such core-cell type functions are also termed xe2x80x9ccore-cell-based ASICs.xe2x80x9d
After the ASIC has been designed and manufactured, the chip must be tested for any manufacturing defects. This involves first simulating the ASIC using a variety of input test patterns, and recording the simulation output results which represent the expected outputs of a properly functioning ASIC. The input test patterns are then applied to the actual ASIC. The actual outputs are compared to the expected outputs. Deviations from the expected outputs indicate that the ASIC has a manufacturing defect.
Tools for evaluating application specific integrated circuits (ASICs) are well known. For example, xe2x80x9cDESIGN COMPILERxe2x80x9d is an ASIC tool commonly used for synthesizing and evaluating the logic and timing of an ASIC, such as by calculating the delay along all paths through the ASIC. Similarly, for ASIC designs that have already been verified through simulation, verification of changes can be accomplished using formal verification tools such as xe2x80x9cFORMALITY.xe2x80x9d Currently available ASIC tools, such as xe2x80x9cDESIGN COMPILERxe2x80x9d and xe2x80x9cFORMALITYxe2x80x9d are adequate for evaluating ASICs, but not for evaluating higher level systems such as circuit board assemblies, or backplanes. xe2x80x9cDESIGN COMPILERxe2x80x9d and xe2x80x9cFORMALITYxe2x80x9d are trademarks of Synopsys, Inc., of Mountain View, Calif.
Board delay calculations, for example, typically involve adding the delay within or through board elements (e.g., ASICs, buffers, RAMs, connectors, etc.) to the delay of connections between those elements (e.g., board routing, backplane routing). Board or backplane timing analysis usually requires a tool other than an ASIC tool. This involves acquisition time and cost, installation, training, experimentation, and verification of results. Hence, board/backplane timing analysis is often done manually, with paper and pencil, calculators, or a spreadsheet. For the same reasons, the paths that are actually analyzed are only a small subset of all the paths that exist. This subset is usually selected in an attempt to analyze the worst paths. This is not a safe, reliable, comprehensive method to employ.
Board designs based in well known hardware description languages (HDLs), such as Verilog or VHDL for example, are becoming more common place as rapid go-to-market strategies demand portability and ease of re-use. As with ASICs, a bug-free design is dependent on the synthesis tool and the quality of an Engineering Change Order (ECO) process. Synthesis tools are well proven for ASIC evaluation, but not for the evaluation of boards, backplanes, or other higher level systems of electronic components. Moreover, the ECO process is somewhat manual and therefore flawed by design. Again, boards are similar to ASICs in that much effort and time go into logic placement and timed route. After this point an ECO is nearly always verified in VHDL and then implemented via a manual edit of the board netlist. Quite often this edit process creates a result that is not logically equivalent to that verified in VHDL.
Typically, ASIC designers use sophisticated synthesis, logic verification, and timing tools throughout the ASIC design process. Ever increasing sophistication of modern board/backplane designs, however, brings the need for tools of similar abilities to those used for ASIC timing and verification. Board/backplane timing analysis tools are less sophisticated and board logic verification tools are nonexistent. Thus, there is a need in the art for a method that provides reliable, efficient synthesis, logic verification, and timing analyses for boards, backplanes, and other high level systems of interconnected electronic components.
The present invention satisfies these needs in the art by providing methods for evaluating a system of electronic components. According to the present invention, an ASIC evaluation tool is used to evaluate systems of electronic components such as circuit board assemblies, backplanes, chassis, racks, etc. To analyze a board, backplane or other higher level system of electronic components, the designer uses information learned from the ASIC evaluation and combines this information with additional data corresponding to the other components that form the system. The combined data is formatted into a format the ASIC evaluation tool understands. In this way, the ASIC evaluation tool is xe2x80x9ctrickedxe2x80x9d into believing that it is evaluating an ASIC when, in reality, it is evaluating a system of electronic components, such as a board or backplane.
According to the methods of the present invention, a designer generates a model library that includes a library element model for each electronic component in the system. The library element models are formatted to be input to an ASIC evaluation tool of the kind described above. The ASIC evaluation tool can be a timing analysis tool, a delay calculation tool, a formal verification tool, or the like, depending on the evaluation the designer wishes to perform. The library element models can be formatted in Verilog or VHDL, for example, or in any other format, depending on the ASIC evaluation tool being used.
The designer then generates a system netlist that represents the system of electronic components, along with the interconnections between the electronic components that form the system. The model library and system netlist are input into the ASIC evaluation tool to evaluate the system. Because the inputs are formatted in a format the ASIC evaluation tool recognizes, the ASIC evaluation tool sees the inputs as it would see the inputs for an ASIC. In this way, the designer practicing a method according to the present invention xe2x80x9ctricksxe2x80x9d the ASIC evaluation tool into believing that it is evaluating an ASIC, when it is, in reality, evaluating a higher level system such as a circuit board assembly, or backplane, etc.